Curriculum Vitæ

I was responsible for the operational success of all the projects being run out of the Manchester Design Centre. To that end all the project managers reported into me, there being 3 $1M+ ASIC design service projects and two smaller ones running concurrently at the peak time. 

I introduced a process oriented approach to the business of the centre and have architected a quality management system for adoption within the centre. I have started to manage the implementation of this system, as an activity subordinate to revenue-earning projects. 

I managed the interface with ICL offering developmental and diagnostic support to the systems integration and field support for their recent mainframe processor product. In a number of instances this was pivotal in securing acceptance of the customer's product with their customer.

Responsible for the design, specification, implementation, and integration of the Storage Systems (including caches and virtual memory architecture) for the latest mainframe computer system (code-name Surrey). 5 team leaders reported to me. 

I supervised the development of the Surrey Memory system. This is an 80 man-year development culminating in the manufacture by the vendor of 3 semi-custom million+ transistor 0.35mm designs. 

I negotiated the specification of a common 512 MB RAM store module and controller chip-set with Fujitsu for use by both companies despite considerable differences in design methodology and culture between the two companies. This saved ICL approximately 10 man-years in bespoke development costs. 

I devised the high-level development route enabling the Surrey hardware to be modelled in ICL's CHISLE specification language. This achieved the billion cycle simulation required to validate the ASIC designs, so reducing the expected rework costs.

Member of the team defining the architecture of the Surrey node, and responsible for the specification of the processor and multiple access cached storage system. 

I identified several bottlenecks in processor performance and suggested changes to the low-level instruction set to improve performance at no extra design cost. 

I specified the modelling of cache coherency protocols which proved the design of the hardware to provide a coherent cached storage system across a multi-processor system.

Responsible for the design, specification and implementation of the Essex processor from initial design requirements to released chip design. I supervised the development of 3 sub-systems of the Essex processor, with three subordinate team leaders. This resulted in the manufacture of about 30 gate-array (12000 transistors each) designs. 

I devised the modelling phases of the development route used which resulted in improved quality (an order of magnitude better than previously and 4 times the comparable Fujitsu product - M760) measured by cost of rework. 

I am named on 3 patents relating to the OCP instruction pipeline control.

Responsible for the design and implementation of the Series 39, Level 80 Arithmetic Unit from specification to released designs. With a team of 8 engineers, I developed approximately 40 ECL gate-array (1600 transistors each) designs.

 Designed and implemented increasingly large subsystems in a series of processor developments from SSI/PCB designs to first generation ECL gate-array designs.